Semiconductor device including dummy gate patterns and manufacturing method thereof

ABSTRACT

A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.

CROSS-REFERENCE TO THE RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35U.S.C. § 119 to and the benefit of Korean Patent Application No.10-2019-0047578, filed on Apr. 23, 2019, in the Korean IntellectualProperty Office (KIPO), the disclosure of which is incorporated hereinby reference in its entirety.

BACKGROUND 1. Field

The present inventive concept relates to a semiconductor deviceincluding gate patterns and a manufacturing method thereof.

2. Description of Related Art

Dummy patterns may be formed in a partial region of a substrate toincrease pattern density and patternability. However, undercuts mayoccur in the dummy patterns, or the dummy patterns may be formed in anasymmetrical shape. Such unstable dummy patterns may act as a defectsource in subsequent processes.

SUMMARY

The present inventive concept is directed to providing a semiconductordevice including a stable dummy pattern.

In addition, the present inventive concept is directed to providing amethod of manufacturing a semiconductor device on which the stable dummypattern is formed.

According to an example embodiment, the disclosure is directed to asemiconductor device comprising: a dummy gate structure including afirst gate pattern in which first dummy gate lines extending in a firstdirection are connected to each other on a substrate, and a second gatepattern in which second dummy gate lines extending in the firstdirection are connected to each other, the second dummy gate lines beingaligned with the first dummy gate lines; and a third gate patternextending in the first direction in parallel with the dummy gatestructure on a first side of the dummy gate structure.

According to an example embodiment, the disclosure is directed to asemiconductor device comprising: a cell region including active finsextending in a first direction and real gate lines extending in a seconddirection, which intersects the first direction, and crossing the activefins; and a dummy region on which dummy gate structures extending inparallel with the real gate lines are disposed, wherein the dummy gatestructures include: a pair of upper dummy gate lines extending in thesecond direction and disposed in parallel with each other; an upperbridge pattern connecting the pair of upper dummy gate lines to eachother; a pair of lower dummy gate lines disposed to be spaced apart fromthe pair of upper dummy gate lines and the upper bridge pattern in thesecond direction; and a lower bridge pattern connecting the pair oflower dummy gate lines to each other.

According to an example embodiment, the disclosure is directed to asemiconductor device comprising: a first gate pattern extending in afirst direction on a substrate; and a second gate pattern disposedadjacent to the first gate pattern in the first direction, wherein thefirst gate pattern comprises a first protrusion in which an innersidewall of the first gate pattern, which is adjacent to the second gatepattern, protrudes toward the second gate pattern, and wherein thesecond gate pattern comprises a second protrusion in which an innersidewall of the second gate pattern, which is adjacent to the first gatepattern, protrudes toward the first protrusion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 1B is a plan view of a partial region of FIG. 1A.

FIG. 2A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 2B is a plan view of a partial region of FIG. 2A.

FIG. 3A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 3B is a plan view of a partial region of FIG. 3A.

FIG. 4A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 4B is a plan view of a partial region of FIG. 4A.

FIG. 5A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 5B is a plan view of a partial region of FIG. 5A FIG. 6A is alayout diagram for describing a semiconductor device according to anexample embodiment of the present inventive concept.

FIG. 6B is a cross-sectional view taken along line A-A′ of FIG. 6A.

FIG. 6C is a cross-sectional view taken along line B-B′ of FIG. 6A.

FIG. 7 is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 8A is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 8B is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIG. 8C is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.

FIGS. 9 to 16 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept.

FIGS. 17 to 19 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept.

FIGS. 20 to 22 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept.

FIGS. 23 to 25 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept.

FIGS. 26 and 27 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Hereinafter, example embodiments of the inventive concept will bedescribed in detail with reference to the accompanying drawings toclearly explain the technical idea of the inventive concept.

FIG. 1A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.FIG. 1B is a plan view of a partial region of FIG. 1A.

Referring to FIGS. 1A and 1B, the semiconductor device according to theexample embodiment of the present inventive concept may include aplurality of gate patterns GP1, GP2, GP3, and GP4 on a substrate. Thegate patterns GP1, GP2, GP3, and GP4 may include a first gate patternGP1 and a second gate pattern GP2. The gate patterns GP1, GP2, GP3, andGP4 may include a conductive material. However, the present inventiveconcept is not limited thereto, and the gate patterns GP1, GP2, GP3, andGP4 may be made of a non-metal material such as polysilicon. Further,the gate patterns GP1, GP2, GP3, and GP4 may be a laminate of a metalelectrode and a silicon electrode, but the present inventive concept isnot limited thereto. For example, the metal electrode may include TiN,and the silicon electrode may include polysilicon.

The first gate pattern GP1 and the second gate pattern GP2 form onepair, and in the present specification, the pair of first gate patternGP1 and second gate pattern GP2 may be referred to as a dummy gatestructure. The first gate pattern GP1 may be referred to as an upperdummy gate structure and the second gate pattern GP2 may be referred toas a lower dummy gate structure.

The gate patterns GP1, GP2, GP3, and GP4 may include a line-shaped thirdgate pattern GP3 disposed on one side of each of the first gate patternGP1 and the second gate pattern GP2, and a line-shaped fourth gatepattern GP4 disposed on the other side of each of the first gate patternGP1 and the second gate pattern GP2. The third gate pattern GP3 and thefourth gate pattern GP4 may extend in parallel with the dummy gatestructure and with one another. In the example embodiment, at least oneof the third gate pattern GP3 and the fourth gate pattern GP4 may be areal gate line that intersects active fins to form a transistor.

The first gate pattern GP1 and the second gate pattern GP2 may bedisposed to be spaced apart from each other. The first gate pattern GP1may include a first gate line GE1, a second gate line GE2, and a firstbridge pattern BR1. The second gate pattern GP2 may include a third gateline GE3, a fourth gate line GE4, and a second bridge pattern BR2.

The first gate line GE1 and the second gate line GE2 may each extendlengthwise in a first direction D1 (a longitudinal direction). An item,layer, or portion of an item or layer described as extending“lengthwise” in a particular direction has a length in the particulardirection and a width perpendicular to that direction, where the lengthis greater than the width. The first gate line GE1 and the second gateline GE2 may be disposed to be spaced apart from each other in a seconddirection D2 (a transverse direction) that intersects the firstdirection D1. The first direction D1 may be orthogonal to the seconddirection D2. The first bridge pattern BR1 may extend in the seconddirection D2 between the first gate line GE1 and the second gate lineGE2 to connect the first gate line GE1 to the second gate line GE2.

One end of the first bridge pattern BR1 may be connected to one end ofthe first gate line GE1, and the other end of the first bridge patternBR1 may be connected to one end of the second gate line GE2. The firstgate line GE1, the second gate line GE2, and the first bridge patternBR1 may be connected to each other to form the first gate pattern GP1having a U-shape. Upper surfaces of the first gate line GE1, the secondgate line GE2, and the first bridge pattern BR1 may be positionedsubstantially on the same plane.

The third gate line GE3 and the fourth gate line GE4 may each extendlengthwise in the first direction D1. The third gate line GE3 and thefourth gate line GE4 may be disposed to be spaced apart from each otherin the second direction D2 that intersects the first direction D1. Thethird gate line GE3 may be spaced apart from the first gate line GE1 inthe first direction D1 and disposed substantially on the same line. Forexample, the first gate line GE1 and the third gate line GE3 may bealigned in the first direction D1. The fourth gate line GE4 may bespaced apart from the second gate line GE2 in the first direction D1 anddisposed substantially on the same line. For example, the second gateline GE2 and the fourth gate line GE4 may be aligned in the firstdirection D1.

The second bridge pattern BR2 may extend in the second direction D2between the third gate line GE3 and the fourth gate line GE4 to connectthe third gate line GE3 to the fourth gate line GE4. One end of thesecond bridge pattern BR2 may be connected to one end of the third gateline GE3 and the other end of the second bridge pattern BR2 may beconnected to one end of the fourth gate line GE4. The third gate lineGE3, the fourth gate line GE4, and the second bridge pattern BR2 may beconnected to each other to form the second gate pattern GP2 having aninverted-U shape. The second gate pattern GP2 may be symmetrical to thefirst gate pattern GP1. Upper surfaces of the third gate line GE3, thefourth gate line GE4, and the second bridge pattern BR2 may bepositioned on the same plane. The second bridge pattern BR2 may bedisposed parallel to the first bridge pattern BR1 in the first directionD1. The second bridge pattern BR2 may be disposed adjacent to the firstbridge pattern BR1. One side surface of the first bridge pattern BR1 andone side surface of the second bridge pattern BR2 may be spaced apartfrom and face each other in the first direction D1. In the exampleembodiment, a width w1 of the first gate line GE1, a width w2 of thesecond gate line GE2, a width w3 of the third gate line GE3, a width w4of the fourth gate pattern GP4, a width w5 of the third gate patternGP3, and a width w6 of the fourth gate pattern GP4 may be substantiallyequal to each other. A width wr1 of the first bridge pattern BR1 and awidth wr2 of the second bridge pattern BR2 may be substantially equal toeach other. The width wr1 of the first bridge pattern BR1 and the widthwr2 of the second bridge pattern BR2 may be substantially equal to thewidths w1, w2, w3, and w4 of the gate lines GE1, GE2, GE3, and GE4 andthe widths w5 and w6 of the third and fourth gate patterns GP3 and GP4.Alternatively, at least one of the width wr1 of the first bridge patternBR1 and the width wr2 of the second bridge pattern BR2 may be differentfrom the widths of the gate lines GE1, GE2, GE3, and GE4.

The first bridge pattern BR1 may be integrally formed with the firstgate line GE1 and the second gate line GE2, and may include the samematerial. For example, the first bridge pattern BR1, the first gate lineGE1, and the second gate line GE2 may be in material continuity with oneanother. The second bridge pattern BR2 may be integrally formed with thethird gate line GE3 and the fourth gate line GE4, and may include thesame material. For example, the second bridge pattern BR2, the thirdgate line GE3, and the fourth gate line GE4 may be in materialcontinuity with one another. As used herein, the terms “materialcontinuity” and “materially in continuity” may refer to structures,patterns, and/or layers that are formed at the same time and of the samematerial, without a break in the continuity of the material of whichthey are formed. As one example, structures, patterns, and/or layersthat are in “material continuity” or “materially in continuity” may behomogeneous monolithic structures.

Vertical cross-sectional shapes of the first gate pattern GP1 and thesecond gate pattern GP2 are illustrated in the drawing (refer to FIG.1A) as being rectangular, but the present inventive concept is notlimited thereto. The cross-sectional shapes of the first gate patternGP1 and the second gate pattern GP2 may have a tapered shape whose widthincreases from an upper portion to a lower portion. Alternatively, thecross-sectional shapes of the first gate pattern GP1 and the second gatepattern GP2 may have a chamfered shape with rounded corners.

FIG. 2A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.FIG. 2B is a plan view of a partial region of FIG. 2A. In FIGS. 1A to2B, the same reference numerals may represent the same components. Aredundant description with the previously-described description will beomitted for the brevity of the description.

Referring to FIGS. 2A and 2B, the semiconductor device may include afirst gate pattern GP1 and a second gate pattern GP2. Further, thesemiconductor device may also include line-shaped third to sixth gatepatterns GP3, GP4, GP5, and GP6 disposed on both sides of the first gatepattern GP1 and the second gate pattern GP2. As described above withreference to FIG. 1B, the first gate pattern GP1 may include a firstgate line GE1, a second gate line GE2, and a first bridge pattern BR1.The second gate pattern GP2 may include a third gate line GE3, a fourthgate line GE4, and a second bridge pattern BR2.

In the example embodiment, a planar shape of the first bridge patternBR1 may have a curved U-shape or inverted-arch shape. A planar shape ofthe second bridge pattern BR2 may have a curved inverted-U shape or archshape. The first bridge pattern BR1 and the second bridge pattern BR2may be symmetrical to each other. A width of at least a portion of thefirst bridge pattern BR1 may be substantially equal to a width of thefirst gate line GE1 and/or a width of the second gate line GE2. A widthof at least a portion of the second bridge pattern BR2 may besubstantially equal to a width of the third gate line GE3 and/or a widthof the fourth gate line GE4. In the example embodiment, in the firstbridge pattern BR1, a portion near the second bridge pattern BR2 mayhave a greater width than a portion relatively far from the secondbridge pattern BR2. For example, in the first bridge pattern BR1, awidth Wb of a center portion may be thicker than a width Wa1 of theother portions. Further, in the second bridge pattern BR2, a portionnear the first bridge pattern BR1 may have a greater width than aportion relatively far from the first bridge pattern BR1. For example,in the second bridge pattern BR2, a width Wc of a center portion may bethicker than a width Wa2 of the other portions. In the exampleembodiment, the width of the first bridge pattern BR1 may be graduallynarrower from a portion closest to the second bridge pattern BR2 towardthe first gate line GE1 or the second gate line GE2. In someembodiments, at boundaries of the first bridge pattern BR1 and the firstand second gate lines GE1 and GE2, the width of the first bridge patternBR1 may be the same as widths of the first and second gate lines GE1 andGE2. The width of the second bridge pattern BR2 may be graduallynarrower from a portion closest to the first bridge pattern BR1 towardthe third gate line GE3 or the fourth gate line GE4. In someembodiments, at boundaries of the second bridge pattern BR2 and thethird and fourth gate lines GE3 and GE4, the width of the second bridgepattern BR2 may be the same as widths of the third and fourth gate linesGE3 and GE4.

FIG. 3A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.FIG. 3B is a plan view of a partial region of FIG. 3A. In FIGS. 1A to3B, the same reference numerals may represent the same components. Aredundant description with the previously-described description will beomitted for the brevity of the description.

Referring to FIGS. 3A and 3B, the semiconductor device may include afirst gate pattern GP1 and a second gate pattern GP2. The semiconductordevice may include a third gate pattern GP3 and a fourth gate patternGP4 disposed on one side of the first gate pattern GP1 and on one sideof the second gate pattern GP2, respectively. The first gate pattern GP1may include a first protrusion PA1 and a first recess DE1. The secondgate pattern GP2 may include a second protrusion PA2 and a second recessDE2.

The first protrusion PA1 may be formed to protrude from an innersidewall of the first gate pattern GP1 toward the second gate patternGP2, facing one sidewall of the second gate pattern GP2. An outersidewall of the first gate pattern GP1 may be concavely recessed towardthe inner sidewall to form the first recess DE1. The first recess DE1may be formed at a position corresponding to the first protrusion PA1 ina first direction D1. In the example embodiment, a width of the firstprotrusion PA1 in a second direction D2 may substantially correspond toa width of the first recess DE1 in the second direction D2. A length ofthe first protrusion PA1 in the first direction D1 may be greater than alength of the first recess DE1 in the first direction D1.

The second protrusion PA2 may be formed to protrude from an innersidewall of the second gate pattern GP2 toward the first gate patternGP1, facing the inner sidewall of the first gate pattern GP1. The secondprotrusion PA2 may be formed at a position corresponding to the firstprotrusion PA1 in the first direction D1 and may extend in the seconddirection D2 toward the first protrusion PA1. An outer sidewall of thesecond gate pattern GP2 may be concavely recessed toward the innersidewall to form the second recess DE2. The second protrusion PA2 andthe second recess DE2 may be symmetrical to the first protrusion PA1 andthe first recess DE1, respectively.

FIG. 4A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.FIG. 4B is a plan view of a partial region of FIG. 4A. In FIGS. 1A to4B, the same reference numerals may represent the same components. Aredundant description with the previously-described description will beomitted for the brevity of the description.

Referring to FIGS. 4A and 4B, the semiconductor device may include afirst gate pattern GP1, a second gate pattern GP2, and a gate bridgepattern GRE. In some embodiments, the first gate pattern GP1, the secondgate pattern GP2, and the gate bridge pattern GRE may be in materialcontinuity with one another. The semiconductor device may include athird gate pattern GP3 disposed on one side of each of the first gatepattern GP1, the second gate pattern GP2, and the gate bridge patternGRE, and a fourth gate pattern GP4 disposed on the other side of each ofthe first gate pattern GP1, the second gate pattern GP2, and the gatebridge pattern GRE. The first gate pattern GP1 may include a first gateline GE1, a second gate line GE2, and a first bridge pattern BR1. Thesecond gate pattern GP2 may include a third gate line GE3, a fourth gateline GE4, and a second bridge pattern BR2. The gate bridge pattern GREmay be referred to as a third bridge pattern BR3. The first gate patternGP1 and the second gate pattern GP2 may have the same or similarconfiguration as those described with reference to FIGS. 1A and 1B.

The gate bridge pattern GRE may be disposed between the first gatepattern GP1 and the second gate pattern GP2. The gate bridge pattern GREmay be disposed between the first bridge pattern BR1 and the secondbridge pattern BR2. The gate bridge pattern GRE may connect the firstgate pattern GP1 to the second gate pattern GP2. The gate bridge patternGRE may connect the first bridge pattern BR1 to the second bridgepattern BR2. In the gate bridge pattern GRE, one side may be in contactwith at least a portion of the first bridge pattern BR1, and the otherside may be in contact with at least a portion of the second bridgepattern BR2. A width We of the gate bridge pattern GRE in a seconddirection D2 may be smaller than a width Wbr of the first and secondbridge patterns BR1 and BR2 in the second direction D2. In the exampleembodiment, the width We of the gate bridge pattern GRE in the seconddirection D2 may be greater than a width Wg of the first gate line GE1in the second direction D2. For example, the width We of the gate bridgepattern GRE in the second direction D2 may be twice or more the width Wgof the gate lines GE1, GE2, GE3, and GE4 in the second direction D2.However, the present inventive concept is not limited thereto.

The first gate pattern GP1, the second gate pattern GP2, and the gatebridge pattern GRE may be integrally formed. Alternatively, the firstgate pattern GP1, the second gate pattern GP2, and the gate bridgepattern GRE may be formed by connecting the first gate pattern GP1 andthe second gate pattern GP2, which are illustrated in FIGS. 3A and 3B.For example, the first gate pattern GP1, the second gate pattern GP2,and the gate bridge pattern GRE illustrated in the FIGS. 4A and 4B maybe formed when a first protrusion PA1 of the first gate pattern GP1 isin contact with a second protrusion PA2 of the second gate pattern GP2.

FIG. 5A is a perspective view for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.FIG. 5B is a plan view of a partial region of FIG. 5A. In FIGS. 1A to5B, the same reference numerals may represent the same components. Aredundant description with the previously-described description will beomitted for the brevity of the description.

Referring to FIGS. 5A and 5B, the semiconductor device may include afirst gate pattern GP1, a second gate pattern GP2, a gate bridge patternBRX, a third gate pattern GP3, and a fourth gate pattern GP4 on asubstrate. In the present specification, the gate bridge pattern BRX mayalso be referred to as a bridge pattern or a third bridge pattern. Thefirst gate pattern GP1 may include a first gate line GE1 and a secondgate line GE2 extending lengthwise in a first direction D1 and inparallel with each other in the first direction D1. The second gatepattern GP2 may include a third gate line GE3 and a fourth gate line GE4extending lengthwise in the first direction D1 and in parallel with eachother in the first direction D1.

The gate bridge pattern BRX may be disposed between the first gatepattern GP1 and the second gate pattern GP2. The gate bridge pattern BRXmay connect the first gate line GE1, the second gate line GE2, the thirdgate line GE3, and the fourth gate line GE4. The gate bridge pattern BRXmay have an X-shape. The gate bridge pattern BRX may include a firstouter sidewall S1, a second outer sidewall S2, a first inner sidewallS3, and a second inner sidewall S4. The first outer sidewall S1 mayextend in the first direction D1 to connect an outer sidewall of thefirst gate line GE1 to an outer sidewall of the third gate line GE3. Thesecond outer sidewall S2 may extend in the first direction D1 to connectan outer sidewall of the second gate line GE2 to an outer sidewall ofthe fourth gate line GE4. The first inner sidewall S3 may connect aninner sidewall of the first gate line GE1 to an inner sidewall of thesecond gate line GE2. For example, the first inner sidewall S3 may havea curved U shape. The second inner sidewall S4 may connect an innersidewall of the third gate line GE3 to an inner sidewall of the fourthgate line GE4. For example, the second inner sidewall S4 may have acurved inverted-U shape.

In the example embodiment, the first outer sidewall S1 may have a curvedsurface recessed toward the inside of the gate bridge pattern BRX. Thesecond outer sidewall S2 may also have a curved surface recessed towardthe inside of the gate bridge pattern BRX. The first inner sidewall S3may have a U-shaped curved surface in which one side thereof extendsinward (rightward) and downward from one end of the first gate line GE1and the other side thereof extends inward (leftward) and downward fromone end of the second gate line GE2. The second inner sidewall S4 mayhave an inverted U-shaped (or arch-shaped) curved surface in which oneside thereof extends inward (rightward) and upward from one end of thethird gate line GE3 and the other side thereof extends inward (leftward)and upward from one end of the fourth gate line GE4.

In the example embodiment, in the gate bridge pattern BRX, the minimumwidth Wh in the first direction D1 may be greater than the minimum widthWx in the second direction D2. In some embodiments, the minimum width Whin the first direction D1 may be the minimum distance between the firstinner sidewall S3 and the second inner sidewall S4. The minimum width Wxof the gate bridge pattern BRX in the second direction D2 may besubstantially equal to or less than twice a width Wg of the gate linesGE1, GE2, GE3, and GE4 in the second direction D2.

FIG. 6A is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept.FIG. 6B is a cross-sectional view taken along line A-A′ of FIG. 6A. FIG.6C is a cross-sectional view taken along line B-B′ of FIG. 6A.

Referring to FIGS. 6A to 6C, the semiconductor device may include afirst region I and a second region II disposed adjacent to the peripheryof the first region I, on a substrate 100. In some embodiments, thesecond region II may be adjacent to the first region I in the seconddirection D2. For example, the first region I may be a cell region, andthe second region II may be a dummy region. In some embodiments, a dummyregion may comprise a region in which no active fins are formed. Thesecond region II may be adjacent to ends of a plurality of parallelactive fins and a border of the first region I and the second region IImay be located between the ends of the active fins and the dummy gatelines disposed closest to the active fins without overlapping the activefins. For example, the border between the second region II and the firstregion I may be defined by the ends of the active fins in the firstregion I (as shown in FIG. 6A).

The semiconductor device may include a device isolation layer 105, aplurality of active fins F1, F2, F3, F4, F5, and F6, a plurality of realgate lines RG1, RG2, and RG3, a plurality of dummy gate lines DG1, DG2,DG3, DG4, DG5, and DG6, bridge patterns BR1, BR2, BR3, and BR4, and aplurality of field gate lines PG. The number of the plurality of activefins F1, F2, F3, F4, F5, and F6, the plurality of real gate lines RG1,RG2, and RG3, the plurality of dummy gate lines DG1, DG2, DG3, DG4, DG5,and DG6, and the plurality of field gate lines PG is not limited by thedrawings, and may be greater or fewer than that illustrated.

A dummy gate line may be a conductive line formed at the same level andadjacent to normal gate lines or electrodes (e.g., normal word lines). Adummy gate line may be patterned from the same conductive layer(s)forming such normal word lines or electrodes. For example, a dummy gateline may be simultaneously formed with normal gate lines with the sameprocesses that deposit and pattern the conductive layer(s) formingnormal word lines. Dummy gate lines in memory devices are not effectiveto cause transmission of data to external devices. For instance, a dummygate line may not be electrically connected to gates of memory cells, orif a dummy gate line is electrically connected to gates of dummy memorycells, such dummy gate lines may not be activated or if activated, maynot result in communication of any data in such dummy memory cells to asource external to the memory device.

The device isolation layer 105 may be disposed on the first region I andthe second region II on the substrate 100. The device isolation layer105 may define the plurality of active fins F1, F2, F3, F4, F5, and F6in the first region I. For example, the device isolation layer 105 mayinclude an oxide.

The plurality of active fins F1, F2, F3, F4, F5, and F6 may be disposedon the substrate 100 in the first region I. The plurality of active finsF1, F2, F3, F4, F5, and F6 may not be disposed on the second region II,which is the dummy region. The plurality of active fins F1, F2, F3, F4,F5, and F6 may protrude in a direction perpendicular to a main surfaceof the substrate 100 (e.g., third direction D3). Upper surfaces of theplurality of active fins F1, F2, F3, F4, F5, and F6 may be positioned ata higher level than an upper surface of the device isolation layer 105.The plurality of active fins F1, F2, F3, F4, F5, and F6 may extendlengthwise in the second direction D2 (a transverse direction) and maybe disposed to be spaced apart from each other in the first direction D1(a longitudinal direction) that intersects the second direction D2. Theplurality of active fins F1, F2, F3, F4, F5, and F6 may be portions ofthe substrate 100 and may include an epitaxial layer grown from thesubstrate 100.

The plurality of real gate lines RG1, RG2, and RG3 may be disposed onthe device isolation layer 105 in the first region I. The plurality ofreal gate lines RG1, RG2, and RG3 may extend lengthwise in the firstdirection D1 in the first region I to cross the plurality of active finsF1, F2, F3, F4, F5, and F6. For example, the plurality of real gatelines RG1, RG2, and RG3 may include a conductive material. For example,the plurality of real gate lines RG1, RG2, and RG3 may include a metal,but the present inventive concept is not limited thereto, and may bemade of a non-metal such as polysilicon. Further, the plurality of realgate lines RG1, RG2, and RG3 may be a laminate of a metal electrode anda silicon electrode, but the present inventive concept is not limitedthereto. For example, the metal electrode may include TiN.

The plurality of dummy gate lines DG1, DG2, DG3, DG4, DG5, and DG6 maybe disposed on the device isolation layer 105 in the first region Iand/or the second region II. The plurality of dummy gate lines DG1, DG2,DG3, DG4, DG5, and DG6 may extend lengthwise in the first direction D1.The plurality of dummy gate lines DG1, DG2, DG3, DG4, DG5, and DG6 maybe disposed to be spaced apart from each other in the second directionD2. The plurality of dummy gate lines DG1, DG2, DG3, DG4, DG5, and DG6may be made of the same materials as the plurality of real gate linesRG1, RG2, and RG3.

In the example embodiment, the plurality of dummy gate lines DG1, DG2,DG3, DG4, DG5, and DG6 may include a first dummy gate line DG1 and athird dummy gate line DG3 disposed on the first region I, and a seconddummy gate line DG2 and a fourth dummy gate line DG4 disposed on thesecond region II.

The first dummy gate line DG1 may be disposed within the first region Iadjacent to the second region II. The second dummy gate line DG2 may bedisposed within the second region II adjacent to the first region I. Thefirst dummy gate line DG1 and the second dummy gate line DG2 may bedisposed adjacent to each other in the second direction D2. In theexample embodiment, the first dummy gate line DG1 may overlap at leastportions of the plurality of active fins F1, F2, F3, F4, F5, and F6.

The third dummy gate line DG3 may be disposed within the first region Iadjacent to the second region II. The third dummy gate line DG3 may bedisposed substantially on the same line as the first dummy gate line DG1and spaced apart from the first dummy gate line DG1 in the firstdirection D1. For example, the first dummy gate line DG1 and the thirddummy gate line DG3 may be aligned in the first direction D1. In theexample embodiment, the third dummy gate line DG3 may overlap at leastportions of the plurality of active fins F1, F2, F3, F4, F5, and F6.

The fourth dummy gate line DG4 may be disposed adjacent to the firstregion I in the second region II. The fourth dummy gate line DG4 may bedisposed adjacent to the third dummy gate line DG3 in the seconddirection D2. The fourth dummy gate line DG4 may be disposedsubstantially on the same line as the second dummy gate line DG2 andspaced apart from the second dummy gate line DG2 in the first directionD1. For example, the third dummy gate line DG3 and the fourth dummy gateline DG4 may be aligned in the first direction D1.

Fifth to eighth dummy gate lines DG5, DG6, DG7, and DG8 may be disposedadjacent to one side of each of the second dummy gate line DG2 and thefourth dummy gate line DG4 in the second region II. The first, second,fifth, and sixth dummy gate lines DG1, DG2, DG5, and DG6 may be referredto as upper dummy gate lines. The third, fourth, seventh, and eighthdummy gate lines DG3, DG4, DG7, and DG8 may be referred to as lowerdummy gate lines.

Each of the bridge patterns BR1, BR2, BR3, and BR4 may extend in thesecond direction D2 in the first region I and/or the second region II torespectively connect a pair of two dummy gate lines, whose longitudinalsidewalls are adjacent to each other, among the plurality of dummy gatelines DG1, DG2, DG3, DG4, DG5, and DG6. A first bridge pattern BR1 maybe connected to the first dummy gate line DG1 and the second dummy gateline DG2 over the first region I and the second region II. A secondbridge pattern BR2 may be connected to the third dummy gate line DG3 andthe fourth dummy gate line DG4 over the first region I and the secondregion II. The first bridge pattern BR1 and the second bridge patternBR2 may be adjacent to each other in the first direction D1. A thirdbridge pattern BR3 may be connected to the fifth dummy gate line DG5 andthe sixth dummy gate line DG6. A fourth bridge pattern BR4 may beconnected to the seventh dummy gate line DG7 and the eighth dummy gateline DG8. The third bridge pattern BR3 and the fourth bridge pattern BR4may be adjacent to each other in the first direction D1. The firstbridge pattern BR1 and the third bridge pattern BR3 may be referred toas upper bridge patterns. The second bridge pattern BR2 and the fourthbridge pattern BR4 may be referred to as lower bridge patterns.

In the example embodiment, at least one of the bridge patterns BR1, BR2,BR3, and BR4 may overlap at least one of the plurality of active finsF1, F2, F3, F4, F5, and F6. In the example embodiment, the first bridgepattern BR1 may overlap a third active fin F3.

The field gate lines PG may extend lengthwise in the first direction D1in the second region II. The field gate lines PG may be gate lineshaving a greater width in the second direction D2 than the real gatelines RG1, RG2, and RG3 or the dummy gate lines DG1, DG2, DG3, DG4, DG5,and DG6. In some embodiments, field gate lines PG may be peripheral gatelines.

The first dummy gate line DG1, the second dummy gate line DG2, and thefirst bridge pattern BR1 illustrated in FIGS. 6A to 6C may correspond tothe first gate pattern GP1 described with reference to FIGS. 1A and 1B.The third dummy gate line DG3, the fourth dummy gate line DG4, and thesecond bridge pattern BR2 illustrated in FIGS. 6A to 6C may correspondto the second gate pattern GP2 described with reference to FIGS. 1A and1B.

FIG. 7 is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept. InFIGS. 6A to 7, the same reference numerals may represent the samecomponents. A redundant description with the previously-describeddescription will be omitted for the brevity of the description.

Referring to FIG. 7, the semiconductor device may include a first regionI and a second region II. The first region I may be a cell region, andthe second region II may be a dummy region. Active fins F and real gatelines RG may be disposed to cross each other in the first region I.Dummy gate structures UDG and DDG and field gate lines PG may bedisposed on the second region II in parallel with each other.

In the example embodiment, the dummy gate structures UDG and DDG may bedisposed in the second region II adjacent to the first region I. Thedummy gate structures UDG and DDG may not overlap the first region I.The dummy gate structures UDG and DDG may be disposed adjacent to oneend of each of the active fins F.

The dummy gate structures UDG and DDG may include an upper dummy gatestructure UDG and a lower dummy gate structure DDG. The upper dummy gatestructure UDG may include a first dummy gate line DG1 and a second dummygate line DG2, which are parallel to each other, and a first bridgepattern BR1 connecting the first dummy gate line DG1 to the second dummygate line DG2. The lower dummy gate structure DDG may include a thirddummy gate line DG3 and a fourth dummy gate line DG4, which are parallelto each other, and a second bridge pattern BR2 connecting the thirddummy gate line DG3 to the fourth dummy gate line DG4.

FIG. 8A is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept. InFIGS. 6A to 8A, the same reference numerals may represent the samecomponents. A redundant description with the previously-describeddescription will be omitted for the brevity of the description.

Referring to FIG. 8A, the semiconductor device may include a firstregion I and a second region II. The first region I may be a cellregion, and the second region II may be a dummy region. The first regionI may include a first cell region AR1 and a second cell region AR2. Thefirst region I may include a middle region CR disposed between the firstcell region AR1 and the second cell region AR2. For example, the middleregion CR may be disposed between adjacent groups of parallel activefins. The middle region CR may not contain any active fins or any memorycells and the width of the middle region CR in the first direction D1may be greater than a pitch of the spacing of the parallel active finsin the first cell region AR1 (i.e., greater than the pitch of thespacing of active fins F3, F2, F1, . . . ) and in the second cell regionAR2 (i.e., greater than the pitch of the spacing of active fins F4, F5,F6 . . . ) (where such pitch may be the same in both the first andsecond cell regions AR1 and AR2). It will also be apparent that thespacing between active fins F3 and F4 (the outermost active fins offirst and second cell regions AR1 and AR2 that are immediately adjacentto each other) in which the middle region CR is formed is larger thanthe spacing between active fins in both the first and second cellregions AR1 and AR2.

First to third active fins F1, F2, and F3 may be disposed on the firstcell region AR1. Fourth to sixth active fins F4, F5, and F6 may bedisposed on the second cell region AR2. However, the number of finsdisposed on the first cell region AR1 and the second cell region AR2 isnot limited by the drawing, and may be greater or fewer than thatillustrated.

Real gate lines RG (e.g., RG1 and RG2) may be disposed on the firstregion I. The real gate lines RG may extend lengthwise in a firstdirection D1 and may be disposed over the first cell region AR1, thesecond cell region AR2, and the middle region CR.

First dummy gate structures UDG1 and DDG1 may be disposed on the firstregion I. The first dummy gate structures UDG1 and DDG1 may include afirst upper dummy gate structure UDG1 and a first lower dummy gatestructure DDG1. At least a portion of the first upper dummy gatestructure UDG1 may be disposed on the first cell region AR1, and atleast a portion of the first lower dummy gate structure DDG1 may bedisposed on the second cell region AR2.

The first upper dummy gate structure UDG1 may include a pair of upperdummy gate lines DG1 and DG2 disposed adjacent to and in parallel witheach other and a first bridge pattern BR1. The first bridge pattern BR1may be referred to as an upper bridge pattern. The pair of upper dummygate lines DG1 and DG2 may include a first dummy gate line DG1 and asecond dummy gate line DG2. The first bridge pattern BR1 may connect oneend of the first dummy gate line DG1 to one end of the second dummy gateline DG2. The first dummy gate line DG1 and the second dummy gate lineDG2 may be disposed on the first cell region AR1 and may extendlengthwise in the first direction D1 to be partially disposed on themiddle region CR. The first bridge pattern BR1 may be disposed on themiddle region CR.

The first lower dummy gate structure DDG1 may include a pair of lowerdummy gate lines DG3 and DG4 disposed adjacent to and in parallel witheach other and a second bridge pattern BR2. The second bridge patternBR2 may be referred to as a lower bridge pattern. The pair of lowerdummy gate lines DG3 and DG4 may include a third dummy gate line DG3 anda fourth dummy gate line DG4. The second bridge pattern BR2 may connectone end of the third dummy gate line DG3 to one end of the fourth dummygate line DG4. The third dummy gate line DG3 and the fourth dummy gateline DG4 may be disposed on the first cell region AR1 and may extendlengthwise in the first direction D1 to be partially disposed on themiddle region CR. The second bridge pattern BR2 may be disposed on themiddle region CR. The second bridge pattern BR2 may be disposed adjacentto and in parallel with the first bridge pattern BR1.

Although the first dummy gate structures UDG1 and DDG1 are illustratedas being disposed on one side of the real gate lines RG in the drawing,in the example embodiment, the first dummy gate structures UDG1 and DDG1may be disposed between the real gate lines RG. For example, the firstdummy gate structures UDG1 and DDG1 may be disposed between a first realgate line RG1 and a second real gate line RG2.

Second dummy gate structures UDG2 and DDG2 may be disposed on the secondregion II, and may include a second upper dummy gate structure UDG2including fifth and sixth dummy gate lines DG5 and DG6 and a thirdbridge pattern BR3 connecting the fifth and sixth dummy gate lines DG5and DG6 to each other. The second dummy gate structures UDG2 and DDG2may include a second lower dummy gate structure DDG2 including seventhand eighth dummy gate lines DG7 and DG8 and a fourth bridge pattern BR4connecting the seventh and eighth dummy gate lines DG7 and DG8 to eachother. For example, the second dummy gate structures UDG2 and DDG2 mayhave the same configuration as the dummy gate structures UDG and DDGdescribed with reference to FIG. 7.

FIG. 8B is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept. InFIGS. 6A to 8B, the same reference numerals may represent the samecomponents. A redundant description with the previously-describeddescription will be omitted for the brevity of the description.

Referring to FIG. 8B, in the semiconductor device, real gate lines RGmay be disposed in a first region I. Dummy gate structures UDG and DDGmay overlap over the first region I and a second region II. The dummygate structures UDG and DDG may include an upper dummy gate structureUDG and a lower dummy gate structure DDG. The upper dummy gate structureUDG may include a first dummy gate line DG1 and a second dummy gate lineDG2, which are a pair of upper dummy gate lines, and a first bridgepattern BR1 connecting the first dummy gate line DG1 to the second dummygate line DG2. The first bridge pattern BR1 may be referred to as anupper bridge pattern. The first dummy gate line DG1 may be disposed on afirst cell region AR1 in the first region I. The first dummy gate lineDG1 may extend lengthwise in a first direction D1 and be partiallydisposed on a middle region CR. The second dummy gate line DG2 may bedisposed on the second region II to be adjacent to the first dummy gateline DG1. The second dummy gate line DG2 and the first dummy gate lineDG1 may be parallel to one another. The first bridge pattern BR1 mayconnect one end of the first dummy gate line DG1 and one end of thesecond dummy gate line DG2 disposed on the middle region CR to eachother. A portion of the first bridge pattern BR1 may be disposed on themiddle region CR in the first region I, and the first bridge pattern BR1may extend in a second direction D2 such that another portion thereofmay be disposed in the second region II.

The lower dummy gate structure DDG may include a third dummy gate lineDG3 and a fourth dummy gate line DG4, which are a pair of lower dummygate lines, and a second bridge pattern BR2 connecting the third dummygate line DG3 to the fourth dummy gate line DG4. The second bridgepattern BR2 may be referred to as a lower bridge pattern. The thirddummy gate line DG3 may be disposed on a second cell region AR2. Thethird dummy gate line DG3 may extend lengthwise in the first directionD1 and be partially disposed on the middle region CR. The fourth dummygate line DG4 may be disposed on the second region II to be adjacent tothe third dummy gate line DG3. The fourth dummy gate line DG4 and thethird dummy gate line DG3 may be parallel to one another. The secondbridge pattern BR2 may extend in the second direction D2 to connect oneend of the third dummy gate line DG3 to one end of the fourth dummy gateline DG4. The second bridge pattern BR2 may be disposed adjacent to thefirst bridge pattern BR1. A portion of the second bridge pattern BR2 maybe disposed on the middle region CR of the first region I and anotherportion thereof may be disposed on the second region II.

In the example embodiment, the semiconductor device may further includeat least one fifth dummy gate line DG5 between the dummy gate structuresUDG and DDG and the field gate PG in the second region II. The fifthdummy gate line DG5 may extend lengthwise in the first direction D1.

FIG. 8C is a layout diagram for describing a semiconductor deviceaccording to an example embodiment of the present inventive concept. InFIGS. 6A to 8C, the same reference numerals may represent the samecomponents. A redundant description with the previously-describeddescription will be omitted for the brevity of the description.

Referring to FIG. 8C, in the example embodiment, a first upper dummygate structure UDG1 is disposed on a first cell region AR1, and a secondupper dummy gate structure UDG2 may be disposed over the first cellregion AR1, a middle region CR, and a second cell region AR2.

A first dummy gate line DG1, a second dummy gate line DG2, and a firstbridge pattern BR1 (an upper bridge pattern) may be disposed on thefirst cell region AR1. A third dummy gate line DG3 and a fourth dummygate line DG4 may extend in a first direction D1 from the second cellregion AR2 to the first cell region AR1 through the middle region CR.The second bridge pattern BR2 (a lower bridge pattern) may connect oneend of the third dummy gate line DG3 to one end of the fourth dummy gateline DG4 in the first cell region AR1.

Although not illustrated in the drawings, the gate patterns and bridgepatterns illustrated in FIGS. 2A to 5B may be disposed on the firstregion I and/or the second region II in the same manner as the exampleembodiments described in FIGS. 6A to 8C. For example, the bridgepatterns BR1, BR2, BR3, and BR4 may have a U-shape or an inverted-Ushape as illustrated in FIGS. 2A and 2B. For example, the upper bridgepattern and the lower bridge pattern may be connected to each other toconnect the upper dummy gate lines to the lower dummy gate lines asillustrated in FIGS. 4A, 4B, 5A, and 5B. The upper bridge pattern andthe lower bridge pattern may be connected to each other to have anX-shape.

FIGS. 9 to 16 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept.

Referring to FIG. 9, a substrate 100 may be a bulk silicon substrate ora silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100may be a silicon substrate, or may include germanium, silicon germanium,indium antimonide, a lead tellurium compound, indium arsenide, indiumphosphide, gallium arsenide, or gallium antimonide, but the presentinventive concept is not limited thereto.

The substrate 100 may include a first region I and a second region II.For example, the first region I may be a cell region, and the secondregion II may be a dummy region, but the present inventive concept isnot limited thereto. The dummy region may include a region in whichdummy patterns are formed to increase pattern density andpatternability. For example, the substrate 100 illustrated in FIG. 9 maybe a partial region of the dummy region. Alternatively, the substrate100 illustrated in FIG. 9 may be a partial region of the cell region.Alternatively, the substrate 100 illustrated in FIG. 9 may be a partialregion overlapping the cell region and the dummy region.

A gate layer 110 may be disposed on the substrate 100. The gate layer110 may include a material, for example, silicon, for forming a gate.For example, the gate layer 110 may include polycrystalline silicon(poly-Si). The gate layer 110 may include a metal material. Although notillustrated in the drawings, a device isolation layer may be furtherincluded between the substrate 100 and the gate layer 110. For example,the device isolation layer may include an oxide.

A first hard mask layer 115 may be disposed on the gate layer 110. Thefirst hard mask layer 115 may include at least one of polysilicon, anoxide, and a nitride. The first hard mask layer 115 may be used to formhard mask patterns for etching gate patterns in subsequent processes.

A mask layer 120 and a second hard mask layer 125 may be disposed on thefirst hard mask layer 115. In the example embodiment, the mask layer 120and the second hard mask layer 125 may have a similar etch selectivity.For example, the mask layer 120 may include polysilicon (for example,P-POLY). The second hard mask layer 125 may include a material similarto that of the first hard mask layer 115. The mask layer 120 and thesecond hard mask layer 125 may be used to form gate mask patterns.

A mandrel layer 130 may be disposed on the second hard mask layer 125.In the example embodiment, the mandrel layer 130 may include a materialsimilar to that of the gate layer 110. The mandrel layer 130 may includea material having a different etch selectivity from that of the secondhard mask layer 125. A double patterning technology (DPT), which uses aspacer disposed on a sidewall of a mandrel pattern as an etch mask, maybe performed in a region in which a fine fin pitch is required.

Referring to FIG. 10, a photoresist pattern 310 may be disposed on themandrel layer 130. In the example embodiment, the photoresist pattern310 may include an H-type pattern. For example, the photoresist pattern310 may include a first line pattern L1 extending lengthwise in thefirst direction D1, a second line pattern L2 extending in parallel withthe first line pattern L1, and a bridge pattern B extending in a seconddirection D2 between the first line pattern L1 and the second linepattern L2 to connect the first line pattern L1 to the second linepattern L2. Further, the photoresist pattern 310 may also include aline-shaped pattern (not shown in the drawing) extending only in thefirst direction D1 without being connected to the bridge pattern B. Insome embodiments, the line-shaped pattern may be two line-shapedpatterns, with a first line-shaped pattern disposed on one side of thefirst line pattern L1 and a second line-shaped pattern on one side ofthe second line pattern L2. The photoresist pattern 310 may be used asan etch mask for etching the mandrel layer 130.

Referring to FIG. 11, a mandrel pattern 132 may be formed by etching themandrel layer 130 using the photoresist pattern 310 as a mask. Themandrel pattern 132 may include an H-type pattern like the photoresistpattern 310. The mandrel pattern 132 may include a first line patternLP1 extending lengthwise in the first direction D1, a second linepattern LP2 extending in parallel with the first line pattern LP1, and abridge pattern BP extending in the second direction D2 between the firstline pattern LP1 and the second line pattern LP2 to connect the firstline pattern LP1 to the second line pattern LP2. The mandrel pattern 132may further include line-shaped patterns (not shown in the drawings)each disposed on one side of the first line pattern LP1 and one side ofthe second line pattern LP2 and extending in the first direction D1.

Referring to FIG. 12, a spacer layer 210L may be disposed on the mandrelpattern 132 and the second hard mask layer 125. The spacer layer 210Lmay conformally cover the mandrel pattern 132 and the second hard masklayer 125. For example, the spacer layer 210L may be formed through anatomic layer deposition (ALD) process. The spacer layer 210L may includea nitride or an oxynitride, but the present inventive concept is notlimited thereto.

Referring to FIGS. 11 to 13, a portion of the spacer layer 210L on thesecond hard mask layer 125 may be removed, and a portion of a topsurface of the second hard mask layer 125 may be exposed. Mandrelspacers 210 positioned on both sidewalls of the mandrel pattern 132 maybe formed. The mandrel spacers 210 are formed, and the mandrel pattern132 may be removed.

In the example embodiment, the mandrel spacers 210 may include outerspacers 210 a and 210 b positioned outside the mandrel pattern 132 andinner spacers 210 c-u, 210 c-d, 210 d-u, 210 d-d, Ba1, and Ba2positioned inside the mandrel pattern 132.

The outer spacers 210 a and 210 b may include a first outer spacer 210 adisposed outside the first line pattern LP1, and a second outer spacer210 b disposed outside the second line pattern LP2. The inner spacers210 c-u, 210 c-d, 210 d-u, 210 d-d, Ba1, and Ba2 may include first innerspacers 210 c-u and 210 c-d disposed adjacent to the first line patternLP1 and second inner spacers 210 d-u and 210 d-d disposed adjacent tothe second line pattern LP2. The inner spacers 210 c-u, 210 c-d, 210d-u, 210 d-d, Ba1, and Ba2 may also include bridge spacer Ba1 connectingthe first inner spacer 210 c-u to the second inner spacer 210 d-u andbridge spacer Ba2 connecting the first inner spacer 210 c-d to thesecond inner spacer 210 d-d.

The first inner spacers 210 c-u and 210 c-d may be divided into a firstupper spacer 210 c-u positioned on an upper side and a first lowerspacer 210 c-d positioned on a lower side with respect to the bridgespacers Ba1 and Ba2. The second inner spacers 210 d-u and 210 d-d may bedivided into a second upper spacer 210 d-u positioned on the upper sideand a second lower spacer 210 d-d positioned on the lower side withrespect to the bridge spacers Ba1 and Ba2.

The bridge spacers Ba1 and Ba2 may include a first bridge spacer Ba1disposed on one side of the bridge pattern BP and a second bridge spacerBa2 disposed on the other side of the bridge pattern BP. The firstbridge spacer Ba1 may connect the first upper spacer 210 c-u to thesecond upper spacer 210 d-u. The second bridge spacer Ba2 may connectthe first lower spacer 210 c-d to the second lower spacer 210 d-d.

The mandrel spacers 210 may be used as a mask for etching the mask layer120 and the second hard mask layer 125. Pattern widths of mask patternsto be obtained by etching the mask layer 120 may be adjusted byadjusting a thickness of the mandrel spacer 210.

Referring to FIG. 14, at least a portion of the second hard mask layer125 may be removed through an etching process in which the mandrelspacers 210 are used as an etch mask. The second hard mask layer 125 maybe etched to form a second hard mask pattern 127 having a shapecorresponding to the mandrel spacer 210.

Referring to FIG. 15, at least portions of the mask layer 120 and thefirst hard mask layer 115 may be removed through an etching process inwhich the mandrel spacer 210 and the second hard mask pattern 127 areused as an etch mask. A first hard mask pattern 117 and a mask pattern122 having shapes corresponding to the mandrel spacer 210 and/or thesecond hard mask pattern 127 may be formed by etching the first hardmask layer 115 and the mask layer 120. The mandrel spacer 210 and thesecond hard mask pattern 127 may be removed in the process of formingthe first hard mask pattern 117 and the mask pattern 122.

Referring to FIG. 16, at least a portion of the gate layer 110 may beremoved through an etching process using the mask pattern 122 and thefirst hard mask pattern 117 as an etch mask. Gate patterns GP1, GP2,GP3, and GP4 having shapes corresponding to the mask pattern 122 and/orthe first hard mask pattern 117 may be formed by etching the gate layer110. The mask pattern 122 may be removed, and a top surface of thesubstrate 100 may be exposed in the process of forming the gate patternsGP1, GP2, GP3, and GP4. The first hard mask pattern 117 may be partiallyetched to have a lower height, thereby forming a hard mask pattern 118.The gate patterns GP1, GP2, GP3, and GP4 illustrated in FIG. 13 maycorrespond to the gate patterns GP1, GP2, GP3, and GP4 illustrated inFIGS. 1A and 1B.

FIGS. 17 to 19 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept. In FIGS. 9 to 19, the same reference numerals denotethe same components. Hereinafter, the contents substantially the same asthose described in FIGS. 1A to 16 will be omitted for the simplicity ofdescription.

Referring to FIG. 17, a photoresist pattern 310 may be disposed on amandrel layer 130. The photoresist pattern 310 may include a first linepattern I1 and a second line pattern I2 that extend in the firstdirection D1 and are disposed on the same line. The first line patternI1 and the second line pattern I2 may be spaced apart from each other ata predetermined interval. The photoresist pattern 310 may include athird line pattern I3 disposed on one side of each of the first linepattern I1 and the second line pattern I2, and a fourth line pattern I4disposed on the other side of each of the first line pattern I1 and thesecond line pattern I2 in the second direction D2.

Referring to FIG. 18, at least a portion of the mandrel layer 130 may beremoved through an etching process using the photoresist pattern 310 asan etch mask. The mandrel layer 130 may be etched to form a mandrelpattern 132. The mandrel pattern 132 may include a plurality of patternscorresponding to the photoresist pattern 310. The mandrel pattern 132may be formed to have a planar shape corresponding to a planar shape ofthe photoresist pattern 310. A spacer layer 210L may conformally coverthe mandrel pattern 132. In the example embodiment, a thickness of thespacer layer 210L may be smaller than half a separation distance betweenthe first line pattern and the second line pattern in the firstdirection D1. A separation space may be left between the first linepattern L1 and the second line pattern L2 even after the spacer layer210L covers the mandrel pattern 132.

Referring to FIG. 19, a portion of a spacer layer 210L on a second hardmask layer 125 may be removed, and a portion of a top surface of thesecond hard mask layer 125 may be exposed. Mandrel spacers 210positioned on both sidewalls of the mandrel pattern 132 may be formed,and the mandrel pattern 132 may be removed.

The mandrel spacers 210 may include a first spacer 211 having a U-shapedplanar shape, a second spacer 212 having an inverted U-shaped planarshape, and line-shaped spacers 213, 214, 215, and 216. In the exampleembodiment, the first spacer 211 and the second spacer 212 may have thesame or similar configuration as the inner spacers 210 c-u, 210 c-d, 210d-u, 210 d-d, Ba1, and Ba2 described with reference to FIG. 10.Subsequently, hard mask patterns and gate patterns corresponding to theplanar shapes of the first spacer 211, the second spacer 212, and theline-shaped spacers 213, 214, 215, and 216 may be formed through thesame or similar process as the etching process performed in the exampleembodiment of FIGS. 11 to 13. The gate patterns as illustrated in FIGS.1A and/or 1B may be formed.

In the example embodiment, although not illustrated in the drawings, themandrel pattern 132, which is formed using the first line pattern I1 andthe second line pattern I2 as an etch mask, may have planar shapesdifferent from planar shapes of the first line pattern I1 and the secondline pattern I2 unlike the description in FIG. 15. For example, a shapebetween the photoresist pattern 310 and the mandrel pattern 132 may bedifferent when the separation distance between the first line pattern I1and the second line pattern I2 is smaller than a process minimum linewidth. Although the first line pattern I1 and the second line pattern I2of the photoresist pattern 310 illustrated in FIG. 17 have planarsurfaces at one end thereof facing each other, one end of the mandrelpattern 132 corresponding to the first line pattern I1 and one end ofthe mandrel pattern 132 facing the one end of the mandrel pattern 132may have curved surfaces rather than planar surfaces. The gate patternformed through the process of using the mandrel pattern having a curvedone end as an etch mask may correspond to the gate pattern described inFIGS. 2A and 2B.

FIGS. 20 to 22 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept. In FIGS. 9 to 22, the same reference numerals denotethe same components. Hereinafter, the contents substantially the same asthose described in FIGS. 1A to 19 will be omitted for the simplicity ofdescription.

Referring to FIG. 20, a photoresist pattern 310 may be disposed on amandrel layer 130. The photoresist pattern 310 may include a first linepattern J1, a second line pattern J2, and a third line pattern J3 thatextend in the first direction D1. The first to third line patterns J1,J2, and J3 may be spaced apart from each other at predeterminedintervals in the second direction D2. In the example embodiment, thefirst line pattern J1 may include notches NC recessed concavely towardthe inside of the first line pattern J1 from both sidewalls of the firstline pattern J1. For example, each of the notches NC may have arectangular shape as illustrated in FIG. 20. Alternatively, the notchesNC may have a V-shape.

Referring to FIG. 21, a mandrel pattern 132 may be formed through anetching process using the photoresist pattern 310 as an etch mask. Themandrel pattern 132 may have a planar shape corresponding to that of thephotoresist pattern 310. For example, a notch may also be formed in themandrel pattern 132. A spacer layer 210L may conformally cover themandrel pattern 132.

Referring to FIG. 22, a portion of the spacer layer 210L may be removed,and mandrel spacers 210 positioned on both sidewalls of the mandrelpattern 132 may be formed. The mandrel spacers 210 are formed, and themandrel pattern 132 may be removed. The mandrel spacers 210 may includefirst to sixth mandrel spacers 221, 222, 223, 224, 225, and 226extending in the first direction D1 and spaced apart from each other inthe second direction D2. A protrusion and a recess may be formed on eachof the first mandrel spacer 221 and the second mandrel spacer 222. Forexample, the shape of a sidewall of the protrusion may correspond to theshape of the notch formed in the mandrel pattern 132. Subsequently, hardmask patterns and gate patterns corresponding to planar shapes of themandrel spacers 210 may be formed through the same or similar process asthe etching process performed in the example embodiment of FIGS. 14 to16. The gate patterns as illustrated in FIGS. 3A and/or 3B may beformed.

FIGS. 23 to 25 are drawings for describing a method of manufacturing asemiconductor device according to an example embodiment of the presentinventive concept. FIGS. 26 and 27 are drawings for describing a methodof manufacturing a semiconductor device according to an exampleembodiment of the present inventive concept. In FIGS. 7 to 27, the samereference numerals denote the same components. Hereinafter, the contentssubstantially the same as those described in FIGS. 1A to 22 will beomitted for the simplicity of description.

Referring to FIG. 23, a photoresist pattern 310 including a first linepattern K1 and a second line pattern K2, which extend in the firstdirection D1, may be formed on a mandrel layer 130. A protrusion PC maybe formed on an inner sidewall of each of the first line pattern K1 andthe second line pattern K2. For example, the protrusions PC may have atriangular or quadrangular shape.

Referring to FIGS. 24 and 25, a mandrel pattern 132 may be formed usingthe photoresist pattern 310. The mandrel pattern 132 may be conformallycovered by a spacer layer 210L. A thickness of the spacer layer 210L maycorrespond to or be greater than half of a separation distance betweenthe protrusion PC of the first line pattern K1 and the protrusion PC ofthe second line pattern K2 in the second direction D2. A space betweenthe protrusion PC of the first line pattern K1 and the protrusion PC ofthe second line pattern K2 may be substantially completely filled by thespacer layer 210L.

A portion of the spacer layer 210L may be removed, and mandrel spacers210 may be formed. The mandrel spacers 210 may include first to fourthmandrel spacers 231, 232, 233, and 234. The first mandrel spacer 231 andthe second mandrel spacer 232 may be in contact with each other. Themandrel pattern 132 may be removed. Subsequently, hard mask patterns andgate patterns corresponding to planar shapes of the mandrel spacers 210may be formed through the same or similar process as the etching processperformed in the example embodiment of FIGS. 14 to 16. The gate patternsas illustrated in FIGS. 4A and/or 4B may be formed.

Referring to FIGS. 26 and 27, in the example embodiment, protrusions PDof mandrel patterns M1 and M2 formed through a process using thephotoresist patterns 310 (K1 and K2), except that each of theprotrusions PC may be a curved surface with rounded side surfaces.Subsequently, mandrel spacers 210 may be formed through a process usingthe mandrel pattern 132, and the gate patterns as illustrated in FIGS.5A and 5B may be formed through a process similar to the etching processperformed in the example embodiment of FIGS. 14 to 16.

According to the example embodiments of the present inventive concept,when dummy gate patterns are formed with a fine pitch, a leaningphenomenon that may occur in the dummy gate patterns can be preventedthrough support parts supporting the dummy gate patterns.

While the embodiments of the present inventive concept have beendescribed with reference to the accompanying drawings, it should beunderstood by those skilled in the art that various modifications may bemade without departing from the scope of the present inventive conceptand without changing essential features thereof. Therefore, theabove-described embodiments should be considered in a descriptive senseonly and not for purposes of limitation.

What is claimed is:
 1. A semiconductor device comprising: a dummy gatestructure including a first gate pattern in which first dummy gate linesextending in a first direction are connected to each other on asubstrate, and a second gate pattern in which second dummy gate linesextending in the first direction are connected to each other, the seconddummy gate lines being aligned with the first dummy gate lines; and athird gate pattern extending in the first direction in parallel with thedummy gate structure on a first side of the dummy gate structure.
 2. Thesemiconductor device of claim 1, wherein the first gate patterncomprises: a first dummy gate line extending in the first direction; asecond dummy gate line disposed in parallel with the first dummy gateline; and a first bridge pattern connecting one end of the first dummygate line to one end of the second dummy gate line; and wherein thesecond gate pattern comprises: a third dummy gate line extending on thesame line as the first dummy gate line; a fourth dummy gate lineextending on the same line as the second dummy gate line, and disposedadjacent to the third dummy gate line; and a second bridge patternconnecting one end of the third dummy gate line to one end of the fourthdummy gate line.
 3. The semiconductor device of claim 2, furthercomprising: a fourth gate pattern extending in the first direction inparallel with the dummy gate structure at a second side of the dummygate structure, wherein at least one of the third gate pattern and thefourth gate pattern is a real gate line.
 4. The semiconductor device ofclaim 2, wherein the first bridge pattern has a U-shape, and wherein thesecond bridge pattern has an inverted U-shape and is symmetrical to thefirst bridge pattern.
 5. The semiconductor device of claim 4, wherein inthe first bridge pattern, a portion nearer the second bridge pattern hasa greater width than a portion farther from the second bridge pattern,and wherein in the second bridge pattern, a portion nearer the firstbridge pattern has a greater width than a portion farther from the firstbridge pattern.
 6. The semiconductor device of claim 2, furthercomprising: a third bridge pattern disposed between the first bridgepattern and the second bridge pattern and connecting the first bridgepattern to the second bridge pattern, wherein a width of the thirdbridge pattern is smaller than a width of the first bridge pattern. 7.The semiconductor device of claim 6, wherein the first, second, andthird bridge patterns are connected to each other to have an X-shape. 8.A semiconductor device comprising: a cell region including active finsextending in a first direction and real gate lines extending in a seconddirection, which intersects the first direction, and crossing the activefins; and a dummy region on which dummy gate structures extending inparallel with the real gate lines are disposed, wherein the dummy gatestructures include: a pair of upper dummy gate lines extending in thesecond direction and disposed in parallel with each other; an upperbridge pattern connecting the pair of upper dummy gate lines to eachother; a pair of lower dummy gate lines disposed to be spaced apart fromthe pair of upper dummy gate lines and the upper bridge pattern in thesecond direction; and a lower bridge pattern connecting the pair oflower dummy gate lines to each other.
 9. The semiconductor device ofclaim 8, wherein a portion of the dummy gate structures overlap the cellregion and the dummy region.
 10. The semiconductor device of claim 8,wherein the pair of upper dummy gate lines comprises: a first dummy gateline disposed on the cell region; and a second dummy gate line disposedon the dummy region, and wherein the upper bridge pattern is disposedover the cell region and the dummy region.
 11. The semiconductor deviceof claim 10, wherein the first dummy gate line crosses the active fins,and the second dummy gate line is disposed adjacent to ends of theactive fins.
 12. The semiconductor device of claim 10, wherein the upperbridge pattern overlaps the active fins.
 13. The semiconductor device ofclaim 8, wherein the cell region comprises: a first cell region on whichfirst active fins are disposed; a second cell region on which secondactive fins are disposed; and a middle region disposed between the firstcell region and the second cell region, and wherein the pair of upperdummy gate lines are disposed on the first cell region, and the pair oflower dummy gate lines are disposed on the second cell region.
 14. Thesemiconductor device of claim 13, wherein the upper bridge pattern andthe lower bridge pattern are disposed on the middle region.
 15. Thesemiconductor device of claim 14, wherein the upper bridge pattern isdisposed on the first cell region, the pair of lower dummy gate linesextend to the first cell region, and the lower bridge pattern isdisposed on the first cell region.
 16. The semiconductor device of claim8, wherein the upper bridge pattern and the lower bridge pattern areconnected to each other.
 17. The semiconductor device of claim 8,wherein the dummy region does not comprise the active fins, and thesemiconductor device further comprises a dummy gate structure disposedon the cell region.
 18. A semiconductor device comprising: a first gatepattern extending in a first direction on a substrate; and a second gatepattern disposed adjacent to the first gate pattern in the firstdirection, wherein the first gate pattern comprises a first protrusionin which an inner sidewall of the first gate pattern, which is adjacentto the second gate pattern, protrudes toward the second gate pattern,and wherein the second gate pattern comprises a second protrusion inwhich an inner sidewall of the second gate pattern, which is adjacent tothe first gate pattern, protrudes toward the first protrusion.
 19. Thesemiconductor device of claim 18, wherein the first gate pattern furthercomprises a first recess in which an outer sidewall is recessedconcavely toward the first protrusion, and wherein the second gatepattern further comprises a second recess in which an outer sidewall isconcavely recessed toward the second protrusion.
 20. The semiconductordevice of claim 19, wherein the first protrusion and the secondprotrusion are in contact with each other.